a) Field of the Invention
The present invention relates to semiconductor devices having MISFETs regularly disposed in a substrate plane.
b) Description of the Related Art
Conventional technologies will be described by taking dynamic random access memories (DRAM) as an example.
FIG. 8 is a schematic plan view of a conventional DRAM. A plurality of word lines 100 are disposed at an equal interval on the surface of a semiconductor substrate, extending along a column direction in FIG. 8. A single dummy word line 101 is disposed on the outer side of the outermost word line 100, extending in the column direction.
A plurality of MISFETs 105 are disposed at positions corresponding to those of the word lines 100 and dummy word line 101. These MISFETs are regularly disposed in the row and column directions. The word lines 100 and dummy word line 101 also serve as the gate electrodes of corresponding MISFETs 105.
Two word lines 100 extend over one active region 104 in which two MISFETs 105 are formed. An interlayer insulating film is formed over the substrate, covering MISFETs 105. A storage contact hole 110 is formed through the interlayer insulating film, for each of storage regions at opposite ends of each active region 104 among the source/drain regions of MISFETs 105. A capacitor is formed in each storage contact hole 110. One electrode of the capacitor is connected to the corresponding storage region 106, and the other electrode constitutes a common electrode of all capacitors.
It is preferable that the storage contact hole 110 is made as large as possible in order to increase a static capacitance of the capacitor. To this end, the storage contact hole 110 is disposed partially overlapping the word line, as viewed along a direction normal to the substrate surface. The capacitor formed in the storage contact hole 110 is electrically insulated from the word line by an insulating film.
Of the source/drain regions of each pair of MISFETs 105, a bit region 107 at the center of the active region 104 is shared by these two MISFETs. A bit contact hole 111 is formed through the interlayer insulating film, for each of the bit regions 107. A bit line 108 extending in the row direction is formed on the interlayer insulating film, in correspondence with each row of bit contact holes. The bit region 107 is connected via a corresponding bit contact hole 111 to the bit line 108.
The word line 100 is connected to a word driver circuit 120. The word driver circuit 120 selectively applies an electrical signal to each word line. More specifically, a voltage Vii is applied to the word line 10 from which column information is read, and a ground voltage Vss is applied to the other word lines 100. The dummy word line 101 is supplied with the ground potential Vss which makes MISFET 105a connected to the dummy word line 101 electrically non-conductive.
An outermost impurity diffusion region 125 extending in the column direction is formed outside of the dummy word line 101 in the substrate surface layer. This outermost impurity diffusion region 125 also functions as the storage region of MISFET 105a corresponding to the dummy word line 101. For example, a voltage Vii/2, which is a half of the Vii applied to the word line 100, is applied to the outermost impurity diffusion region 125. The outermost impurity diffusion region 125 traps electrons generated by the operations of transistors in a peripheral circuit and prevents the electrons from being diffused into the memory cell region.
Each bit line 108 is connected to a sense amplifier circuit 130. The sense amplifier circuit 130 is disposed outside of the outermost impurity diffusion region 125. The sense amplifier circuit 130 detects a voltage on the bit line 108. A bit line 108a on the outermost side (uppermost row in FIG. 8) is not connected to the sense amplifier circuit 130 but is used as a dummy bit line.
The outermost word and bit lines are therefore used as dummy lines. MISFETs corresponding to the dummy word and bit lines do not operate as memory cells. This layout of dummy word and bit lines allows the pattern of regions functioning as actual memory cells to be formed stably.
From the same reason as above, a storage contact hole 110a is also formed above the storage region of MISFET 105a corresponding to the dummy word line 101. Along a bit line 108b at the second row in FIG. 8, a storage contact hole 110b is formed riding on the dummy word line 101 and the outermost impurity diffusion region 125.
FIG. 9 is a cross sectional view taken along one-dot chain line A9--A9. On the surface of the p-type silicon substrate 150, a field oxide film 151 is formed. In a surface layer of an active region defined by the field oxide film 151, the outermost impurity diffusion region 125 is formed having a n-type conductivity doped with phosphorous (P).
The dummy word line 101 is formed on the field oxide film 151 in an area near its end. The dummy word line 101 is a lamination of a polysilicon film 101a and a WSi film 101b. An upper insulating film 152 made of SiO.sub.2 is formed on the WSi film 101b. Side wall insulating films 153 made of SiO.sub.2 are formed on the side walls of the lamination structure of the dummy word line 101 and upper insulating film 152. Namely, the upper side surfaces of the dummy word line 101 are covered with the upper insulating film 152 and side wall insulating film 153 both made of SiO.sub.2.
A protective film 155 made of SiO.sub.2 is formed covering the upper insulating film 152, side wall insulating films 153, and outermost impurity diffusion region 125. On this protective film 155, an etching stopper film 156 made of SiN is formed. On the etching stopper film 156, an interlayer insulating film 157 made of borophosphosilicate glass (BPSG) is formed. The surface of the interlayer insulating film 157 is planarized by chemical mechanical polishing (CMP).
The storage contact hole 110b is formed through the interlayer insulating film 157 to expose the surface of the outermost impurity diffusion region 125. The storage contact hole 110b extends over a partial area of the dummy word line 101. Etching the interlayer insulating film 157 can be stopped with high reproductivity by the etching stopper film 156 made of SiN.
The etching stopper film 156 exposed on the bottom of the storage contact hole 110b is removed. While the etching stopper film 156 is removed, the protective film 155 made of SiO.sub.2 protects the outermost impurity diffusion region 125. The protective film 155 exposed on the bottom of the storage contact hole 110b is finally removed.
A storage electrode 160 made of polysilicon is formed on the bottom and side surfaces of the storage contact hole 110b. The surface of the storage electrode 160 and the upper surface of the interlayer insulating film 162 are covered with a dielectric film 161 made of SiN. The surface of the dielectric film 161 may be oxidized to form a thin SiO film on the surface thereof. A common electrode 162 made of polysilicon is formed on the surface of the dielectric film 161.
The dummy word line 101 and storage electrode 160 are electrically separated by the upper insulating film 152 and side wall insulating films 153. However, if the storage contact hole 110b is over-etched, the dummy word line 101 and storage electrode 160 may contact each other. In this case, the dummy word line 101 and outermost impurity diffusion region 125 are shorted via the storage electrode 160. Since the ground potential Vss is applied to the dummy word line 101 and the voltage Vss/2 is applied to the outermost impurity diffusion region 125, current always flows when both are shorted. In this case, even if the memory cell region has no bit error, a standby current error occurs.